High-performance BiCMOS output buffer design strategies
نویسندگان
چکیده
This paper discusses design issues for high-performance BiCMOS output buffers, as required in T&Hs and data converters for advanced applications. We compare different topologies and analyze the main limitations. The best solution features a linearity better than -105 dB (HD3) at an input frequency of 100 MHz. The simulation results referred to a conventional 0.8 pm BiCMOS process cover a huge range of performance parameters in terms of linearity, bandwidth and dynamic range. More in general, this paper helps the designer to identify the best strategy for given high speed and high resolution specifications. a) b) Figure 1. Schematic diagram of a level-shifter: a) NMOS; b) PMOS 2. SIMPLE CMOS BUFFER
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